Flash memory is replacing hard disks and optical disks as a preferred storage medium. NAND flash memory is a type of flash memory constructed from electrically-erasable programmable read-only memory (EEPROM) cells, which have floating gate transistors. These cells use quantum-mechanical tunnel injection for writing and tunnel release for erasing. NAND flash is non-volatile so it is ideal for portable devices storing data.
However, NAND flash has limitations. In the flash memory cells, the data is stored in binary terms—as ones (1) and zeros (0). One limitation of NAND flash is that when storing data (writing to flash), the flash can only write from ones (1) to zeros (0). When writing from zeros (0) to ones (1), the flash needs to be erased a “block” at a time. Although the smallest unit for read or program can be a byte or a word, the smallest unit for erase is a block.
Single Level Cell (SLC) flash and Multi Level Cell (MLC) flash are two types of NAND flash. The erase block size of SLC flash may be 128K+4K bytes while the erase block size of MLC flash may be 256K+8K bytes. Another limitation is that NAND flash memory has a finite number of erase cycles between 10,000 to 1,000,000, after which the flash wear out and becomes unreliable.
Comparing MLC flash with SLC flash, MLC flash memory has its advantages and disadvantages in consumer applications. In the cell technology, SLC flash stores a single bit of data per cell, whereas MLC flash stores two or more bits of data per cell. MLC flash can have twice or more the density of SLC flash with the same technology. But the performance, reliability and durability may decrease for MLC flash. MLC flash clearly has more storage at a low cost so it gains popularity with consumers. But it has a lower write speed than SLC flash memory, which means that it takes a longer time to store pictures when taking snapshots. Its low performance requires a stronger wear-leveling algorithm to meet consumers' needs. In addition, the life of MLC flash memory is limited to perhaps 10,000 erase cycles. The number of partial programming (NOP) cycles in MLC flash memory is known to be one. This means that the whole block needs to be erased if the system wants to reprogram a page. Therefore, a good wear leveling algorithm is needed to solve the MLC flash reprogramming problem.
A wear leveling algorithm allows the memory controller to remap logical addresses to different physical address so that data writes can be evenly distributed. Thus the wear leveling algorithm extends the endurance of the MLC flash memory.
Block sizes are expected to increase as higher density MLC flash chips become commercially available. However, the size of the host data being stored is not expected to increase at the same rate as the block size. Thus flash blocks are less efficiently used as the flash blocks become larger, but store fixed-size pieces of host data. For example, hosts may send sectors of 512 Kbytes to be stored in larger flash blocks, wasting space in the flash block.
Flash blocks with much unused space may be combined with other such blocks to improve block storage efficiency. However, moving data around among flash blocks increases wear, as flash blocks need to be erased. Paging and disk de-fragmenting methods, which have been used for main DRAM memories and hard disks, are ineffective for flash memory due to the restricted life of flash. Such methods would quickly wear out the flash memory blocks.
A large DRAM or SRAM buffer could be used to merge writes before writing to flash, but if power is lost, the data in the write buffer may also be lost. The size of the write buffer may be prohibitive, especially as flash blocks increase in size, since the write buffer needs to have a size equal to one or more flash blocks.
Larger flash systems may use several channels to allow parallel access, improving performance. However, moving data from one channel to another during wear-leveling may decrease performance.
What is desired is a multi-channel flash system that has improved wear leveling. A MLC flash system is desired that aggregates smaller writes into flash memory so that data is not lost when power fails. A write-aggregating flash system that leverages the multiple channels of flash is desirable.